1. Field of the Invention
The invention relates to a fabricating method of a semiconductor device and more particularly to a fabricating method of a transistor.
2. Description of Related Art
In order to accelerate operating speed of integrated circuit and to meet customers' demands on miniaturizing electronic devices, physical dimensions of transistors in a semiconductor device are continuously reduced. However, as the dimension of the transistor is reduced, its channel length will also decrease with ease leading to problems such as short channel effect, decrease of turn-on current, and increase of leakage current. Accordingly, the reliability of the device is reduced.
Generally, a doped source region and a doped drain region are formed in a substrate at two sides of a gate, and contacts are then formed to electrically connect the doped source region and the doped drain region, respectively. However, with the miniaturization of devices, a serious junction leakage is generated when the distance between the contacts and the doped regions is too short. In detail, as the dimension of the device is minimized, the distance between the doped source region and the doped drain region is reduced and electric field thereof is increased. Therefore, the junction leakage occurs in the doped source region and the doped drain region, and turn on and turn off of the transistor is not controlled by the gate.
In the conventional technique, formation of elevated source and drain is proposed to reduce the junction leakage, that is, a source and a drain having a specific height are respectively formed on the doped source region and the doped drain region, thereby increasing the distance between the contacts and the doped regions. However, since the elevated source and drain are generally formed by filling an epitaxial layer in the openings through a selective epitaxial process, incomplete gap-filling of the epitaxial layer is likely to occur when the dimension of the device is continuously reduced. Accordingly, a thickness of the formed source and drain is not sufficient to prevent the junction leakage of the doped source region and the doped drain region.